The present invention relates generally to integrated circuits, and in particular to graded composition gate insulators to reduce tunneling barriers in Flash memory devices.
Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. As is well known in the art, such a process allows a high degree of integration such that a high circuit density can be obtained with the use of relatively few well-established masking and processing steps. A standard CMOS process is typically used to fabricate FETs that each have a gate electrode that is composed of n-type conductively doped polycrystalline silicon (polysilicon) material or other conductive materials.
Field effect transistors (FETs) are used in many different types of memory devices, including EPROM, EEPROM, EAPROM, DRAM and flash memory devices. They are used as both access transistors, and as memory elements in flash memory devices. In these applications, the gate is electrically isolated from other conductive areas of the transistor by an oxide layer. A drawback with FETs having grown oxide insulators is manifested in the use of Fowler-Nordheim tunneling to implement nonvolatile storage devices, such as in electrically erasable and programmable read only memories (EEPROMs). EEPROM memory cells typically use CMOS floating gate FETs. A floating gate FET typically includes a floating (electrically isolated) gate that controls conduction between source and drain regions of the FET. In such memory cells, data is represented by charge transfer on the floating gates. Fowler-Nordheim tunneling is one method that is used to store charge on the floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation. The high tunneling voltage of grown oxides used to provide such isolation increases the time needed to store charge on the floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation. This is particularly problematic for xe2x80x9cflashxe2x80x9d EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as for use in flash EEPROMs.
Many gate insulators have been tried, such as grown oxides, CVD (chemical vapor deposition) oxides, and deposited layers of silicon nitride, aluminum oxide, tantalum oxide, and titanium oxide with or without grown oxides underneath. The only commonly used gate insulator at the present time is thermally grown silicon oxide. If other insulators are deposited directly on the silicon, high surface state densities result. Composite layers of different insulators are first grown and then deposited, such as oxide-CVD oxide or oxide-CVD nitride combinations. If composite insulators are used, charging at the interface between the insulators results due to trap states at this interface, a bandgap discontinuity, and/or differences in conductivity of the films.
Silicon dioxide is an insulator with a relative dielectric constant 3.9, energy gap xcx9c9 eV, and electron affinity ("khgr") of 0.9 eV. By comparison, the energy gap and electron affinity for the semiconductor silicon are 1.1 eV and 4.1 eV, respectively. In a conventional flash memory, electrons stored on the polysilicon floating gate see a large tunneling barrier of about 3.2 eV. FIG. 1 shows the conventional large 3.2 eV barrier for tunneling erase in flash memory devices. The current during erase is an exponential function of the barrier height and thickness (S. M. Sze, xe2x80x9cPhysics of semiconductor devices,xe2x80x9d Wiley, N.Y., 1981, p. 403). The large 3.2 eV tunneling barrier is the difference between the electron affinities "khgr" of silicon (4.1 eV) and SiO2 (0.9 eV). See FIG. 4. This is a relative large barrier which requires high applied electric fields for electron injection. Even with high applied fields, the erase times are long. The high fields additionally degrade device yield and contribute to various reliability problems including premature gate insulator breakdowns. Such problems stem from the fact that polysilicon gate conductors in combination with an SiO2 and/or Si3N4 dielectrics produces a large barrier height for charge injection and thus do not constitute an optimum combination of materials for flash memories.
Other approaches to resolve the above described problems include; the use of different floating gate materials, e.g. SiC, SiOC, GaN, and GaAIN, which exhibit a lower work function (see FIG. 2A), the use of structured surfaces which increase the localized electric fields (see FIG. 2B), and amorphous SiC gate insulators with larger electron affinity, "khgr", to increase the tunneling probability and reduce erase time (see FIG. 2C).
One example of the use of different floating gate (FIG. 2A) materials is provided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled xe2x80x9cFLASH MEMORY WITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.xe2x80x9d Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes, entitled xe2x80x9cFLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATING GATE.xe2x80x9d Still further examples of this approach are provided in pending applications by L. Forbes and K. Ahn, entitled xe2x80x9cDYNAMIC RANDOM ACCESS MEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOW ELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,xe2x80x9d Ser. No. 08/908098, and xe2x80x9cVARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICON CMOS MEMORIES AND IMAGING DEVICES,xe2x80x9d Ser. No. 08/903452.
An example of the use of the structured surface approach (FIG. 2B) is provided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y. Ahn, entitled xe2x80x9cDRAM CELLS WITH A STRUCTURE SURFACE USING A SELF STRUCTURED MASK.xe2x80x9d Another example is provided in U.S. Pat. No. 6,025,627 by L. Forbes and J. Geusic, entitled xe2x80x9cATOMIC LAYER EXPITAXY GATE INSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.xe2x80x9d
Finally, an example of the use of amorphous SiC gate insulators (FIG. 2C) is provided in U.S. patent application Ser. No. 08/903453 by L. Forbes and K. Ahn, entitled xe2x80x9cGATE INSULATOR FOR SILICON INTEGRATED CIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.xe2x80x9d
Still, there is a need for other improved gate insulators which provides a low tunneling barrier. There is a further need to reduce the tunneling time to speed up storage and retrieval of data in memory devices. There is yet a further need for a gate insulator with less charging at the interface between composite insulator layers. A further need exists to form gate insulators with low surface state densities.
The above mentioned problems with semiconductor memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided which substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier-heights of controlled thicknesses can be formed using SiOx and SixCyOz dielectrics prepared according to the process as described herein.
This disclosure describes the use of the lower band gap and larger electron affinity dielectric materials silicon suboxide (SiOx with 1 greater than x less than 2) and silicon oxycarbide (SixCyOz) in combination with a SiO2 to form composite dielectric flash memory gate insulators. Such structures will have lower effective tunneling barriers and consequently reduce device erase times, other factors being equal.
In one embodiment of the present invention, a flash memory cell is provided. The flash memory cell includes a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes the channel. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. The graded composition gate insulator, or composite gate dielectric structure has a larger electron affinity insulator on top of a silicon dioxide layer underneath the floating gate to reduce the tunneling barrier during erase. A second gate is separated from the first gate by a second gate insulator.